`timescale 1ns / 1ps

module rgmii_receive(
     input         reset,
	 input         RGMII_rx_clk,
	 input         RGMII_rx_ctrl,
	 input [3:0]   RGMII_rx_data,
	 
	 output wire        RGMII_reference_clk,
	 output wire        GMII_data_valid,
	 output wire        GMII_rx_error,
	 output wire[7:0]   GMII_rx_data
);
	 
wire         GMII_rx_valid;
wire         RGMII_rx_valid_xor_error;

assign  GMII_data_valid = GMII_rx_valid;
assign  GMII_rx_error = GMII_rx_valid ^ RGMII_rx_valid_xor_error;  
assign RGMII_reference_clk = RGMII_rx_clk;


EG_LOGIC_IDDR rgmii_rx_ctl_in(
	.q1	(RGMII_rx_valid_xor_error),
	.q0	(GMII_rx_valid),
	.clk(RGMII_rx_clk),
	.d	(RGMII_rx_ctrl),
	.rst(reset)
);

genvar i;
generate for (i=0; i<4; i=i+1)
    begin : RGMII_RX_DATA_BUS
		EG_LOGIC_IDDR rgmii_rx_data_in(
			.q1	(GMII_rx_data[i+4]),
			.q0	(GMII_rx_data[i]),
			.clk(RGMII_rx_clk),
			.d	(RGMII_rx_data[i]),
			.rst(reset)
		);	
   end
endgenerate
	
endmodule
